1. Field of the Invention
The present disclosure relates to amplifier circuits, and more particularly, to amplifier circuits that are robust to variations in a voltage level of an external reference signal or an external input signal.
2. Description of the Related Art
In the semiconductor device field, as data transmission speeds between semiconductor chips is increasing, power consumed in data interfaces is also increasing.
In order to reduce power consumption, an attempt has been made to reduce an operating voltage level. However, it is more difficult for a data receiver to receive data when the operating voltage level is reduced, but noise in the interface is not reduced enough.
In particular, since the speed of the interface increases, the operating voltage level is reduced to prevent increasing power consumption, and a termination circuit is used to reduce noise between signals. Voltage levels of whole signals are reduced, thereby reducing drastically a swing range of an external signal input to an amplifier circuit.
FIG. 1 is a diagram for explaining a reduction in a swing range of an external input signal and variations in a delay time, indicated generally by the reference numeral 100. Referring to FIG. 1, a high level band VIHBAND in which the external input signal is recognized as a high level signal, and a low level band VILBAND in which the external input signal is recognized as a low level signal, are reduced gradually to a point where the bands become narrower than a reference signal band VREFBAND.
If the high level band VIHBAND and the low level band VILBAND are reduced and a level of a reference signal is varied within the reference signal band VREFBAND, a valid window in which the external input signal can be recognized as a high level signal or a low level signal is reduced disadvantageously.
FIG. 2 is a circuit diagram of a conventional amplifier circuit. Referring to FIG. 2, a conventional amplifier circuit 200 includes a bias unit 210, which generates a bias voltage VBIAS having a constant voltage level, and an amplifier unit 220, which responds to the bias voltage VBIAS and outputs amplified data.
The bias unit 210 includes first through fourth transistors TR1, TR2, TR3, and TR4, respectively, which build a current mirror. Since a power voltage VDD is applied to a gate of the third transistor TR3, the third transistor TR3 is always turned on, and accordingly, a gate of the first transistor TR1 changes to a low level due to a ground voltage VSS.
Therefore, the first transistor TR1 and the second transistor TR2 are turned on, and a first node N1 maintains a constant voltage level due to current flowing through the second transistor TR2. At this time, the amount of the current flowing through the second transistor TR2 can be controlled and the voltage level of the first node N1 can also be controlled by adjusting the size of the first transistor TR1 and the second transistor TR2. The voltage at the first node N1 makes the fourth transistor TR4 turn on, and is output as the bias voltage VBIAS. The bias voltage VBIAS output from the bias unit 210 is maintained constant.
The amplifier unit 220 includes fifth through ninth transistors TR5, TR6, TR7, TR8, and TR9, which amplify a voltage difference between an external reference signal XVREF and an external input signal XIN, and output, respectively, data DATA and inverted data DATAB through an output node OUTN and an inverted output node OUTNB.
The fifth transistor TR5 and the sixth transistor TR6 are turned on due to the ground voltage VSS connected to gates thereof, and a degree to which the seventh transistor TR7 and the eighth transistor TR8 are turned on is determined depending on voltage levels of the external reference signal XVREF and the external input signal XIN, respectively input to the fifth transistor TR5 and the sixth transistor TR6. The ninth transistor TR9 responds to the bias voltage VBIAS and determines the whole operation of the amplifier unit 220. That is, if the ninth transistor TR9 is turned on, the amplifier unit 220 operates, and if the ninth TR9 is turned off, the amplifier unit 220 does not operate. If the voltage level of the bias voltage VBIAS applied to the ninth transistor TR9 is constant, swing ranges of the data DATA and the inverted data DATAB output from the amplifier unit 220 are maintained constant.
The operation of the amplifier unit 220 is equal to that of a general differential amplifier, which is well known to one of ordinary skill in the pertinent art, and thus, a detailed explanation thereof will not be given.
FIG. 3A shows a graph 300 illustrating the external input signal and the external reference signal input to the amplifier circuit shown in FIG. 2. FIG. 3B shows a graph 350 illustrating the data output from the amplifier circuit shown in FIG. 2.
Referring to FIG. 3A, the voltage level of the external input signal XIN and the external reference signal XVREF is not constant, but is varied. That is, as the level of the external input signal XIN is varied, the level of the external reference signal XVREF is also varied to 0.55V, 0.75V, and 0.95V.
Accordingly, although the voltage level of the bias voltage VBIAS applied to the ninth transistor TR9 of the amplifier unit 220 is constant, if the level of the external input signal XIN and the level of the external reference signal XVREF are varied as shown in FIG. 3A, the swing ranges of the data DATA and the inverted data DATAB output from the amplifier circuit 200 are not constant and output delay times are increased.
This is because as the voltage levels of the external input signal XIN and the external reference signal XVREF are varied, a voltage level of a second node N2 of the amplifier unit 220 is varied. Referring to FIG. 3B, it can be seen that the swing range of the data DATA is not constant, as is shown by arrows (i), (ii), and (iii). Further, it can be seen that an output delay time TD taken from when data DATA is output to when next data DATA is output is relatively long.
As a result, the conventional amplifier circuit has poor performance in that when the voltage levels of the external input signal XIN and the external reference signal XVREF are varied, the output swing ranges are not constant and the output delay times are increased.